i. Cross-references to related patents and publications
The following references, including patents assigned to the same assignee as the present invention, describe aspects of a data processing system which are particularly adapted for utilizing this invention.
A. U.S. Pat. No. 3,614,741 issued Oct. 19, 1971, and entitled "Data Processing System With Instruction Addresses Identifying One of a Plurality of Registers Including the Program Counter"; PA0 B. U.S. Pat. No. 3,710,324 issued Jan. 9, 1973, and entitled "Data Processing System"; PA0 C. PDP-11 Peripherals and Interfacing Handbook, Digital Equipment Corporation, 1971.
II. Field of the Invention
This invention relates to data processing systems and more specifically to the interconnection of otherwise independently operable digital computer systems.
III. Prior Art
A digital computer system normally includes a central processor unit, a random access memory unit and a number of peripheral units. These units are usually interconnected by some means, such as one or more buses as described in the above-identified U.S. Pat. No. 3,710,324. Generally these units can be designated "system resources."
Some systems include two or more sets of system resources including multiple central processing units. These system resources may then be arranged differently in each set. In one approach the different central processor units may be connected with different resources to form normally independently operable digital computer systems. To achieve improved operating efficiencies, however, it is oftentimes desirable for one set of system resources to be able to use the resources of another set.
For example, one central processor unit and its associated memory and peripheral units may perform arithmetic operations while another set of system resources performs input/output functions. In large multiprocessor systems there may be a library of programs on several disk memory units. In order to improve storage efficiency, it may be desirable to store programs in one set of resources and then allow the other sets to retrieve individual programs as they are needed for processing.
In one interconnecting approach, one memory unit has two "ports" and can be connected to two digital computer systems as a common memory. One system transfers data to a memory location in the multi-port memory which is common to both systems. Then a series of control signals cause the other digital computer system to use that data.
In another approach, a buffer register connects two systems. A first system moves data to the buffer and sends an interrupting signal to the second system. The second system responds to the signal with a program which moves the data in the buffer to a new location and sends another interrupting signal back to the first system. The first system receives the interrupting signal from the second system, notes that the transfer is finished and continues its operation.
These are fairly simple approaches to implement but they have several disadvantages. For one, a program in one system cannot directly address a location in the other system. In systems where peripheral devices have memory addresses, it is not possible to transfer data from one system directly to a peripheral device in another system. Further, such systems perform slower. This is especially true in the second approach because the first system can not continue operating until the returning signal is received from the other system. In both approaches programming is more complex.
In still another approach, an interconnecting circuit provides a data path between the buses in otherwise independently operable data processing systems. Usually such systems have a reserved block of addresses for identifying various registers in different peripheral units. The block is often termed an I/O page, and it resides in memory or is constituted by a range of available peripheral addresses. A fixed number of these locations are assigned to the interconnecting unit. The interconnecting unit reassigns an address and effects a transfer to the other system. In these systems the I/O page comprises a fixed number of locations. Thus, the number of locations is usually limited to only a few locations (e.g., 512 locations). Larger numbers would severely restrict the size of the number of locations in the memory or available for actual input/output operations.
Therefore, it is an object of this invention to provide a unit for interconnecting otherwise independently operable digital computer systems.
Another object of this invention is to provide an interconnecting unit between digital computer systems which enables an instruction in one system to directly address a memory location in the other system.
Yet another object of this invention is to provide an interconnecting unit between two digital computer systems which is relatively simple to implement.